As it is known, a parallel bus comprises a number of parallel physical connections suitable for connecting two communication devices and supporting exchange of data between them. Data transmission is shared among all the physical connections of the parallel bus. The physical connections may be either optical connections (e.g. optical fibers) or electrical connections. Parallel buses are opposed to serial buses, that transport data on a single physical connection.
Communication devices connected by means of a parallel bus have to be equipped with suitable interfaces known as “serdes” (serializer-deserializer). A serdes typically has a transmitting side and a receiver side. At the transmitting side, the serdes has a demultiplexer suitable for receiving an aggregated data flow from a serial bus and for performing a time-division demultiplexing on it for obtaining N parallel data flows, wherein N is lower than or equal to the number of physical connections within the parallel bus (deserialization). Each of the N parallel data flows is then transmitted on a respective physical link of the parallel bus. On the other hand, at the receiving side, the serdes has a multiplexer suitable for receiving N parallel data flows from respective physical connections of a parallel bus, and for performing a time-division multiplexing on them for recovering an aggregated data flow to be transmitted on a serial bus (serialization).
During propagation from the serdes of a first communication device to the serdes of a second communication device, each parallel data flow undergoes a different propagation delay. This may be due for instance to the fact that physical connections have slightly different lengths. Accordingly, bits of different parallel data flows that are transmitted at the same time from the serdes of a first communication device are received at the serdes of the second communication device at different times. This effect is termed “skew”.
Skew is an undesirable effect, since it prevents the parallel data flows from being properly aligned at the receiving side, thereby causing errors in recovering the original sequence of bits of the aggregated data flow. The higher the parallel bus length and the higher the transmission data rate, the higher is the number of errors induced by skew on the recovered aggregated data flow.
The document “Serdes Framer Interface Level 5 (SFI-5): Implementation Agreement for 40 Gb/s Interface for Physical Layer Devices (OIF-SFI5-01.02)”, Jan. 29, 2002, created by OIF (Optical Internetworking Forum), discloses a serdes for transmitting an aggregated optical data flow at 40 Gb/s by means of sixteen physical connections plus a “deskew” physical connection of a parallel bus, that is suitable to implement an alignment mechanism for compensating skew. The same document discloses also a quad serdes for transmitting four independent aggregated optical data flows at 10 Gb/s by means of four parallel buses, each constituted by four physical connections plus a deskew one, named SFI-5s. The operation of this serdes will be now explained by referring to FIGS. 6a and 6b. 
At the transmitting side, an aggregated data flow to be transmitted over the parallel bus is divided into four parallel data flows PF1, PF2, PF3, PF4 by time division demultiplexing. Then, an additional flow AF is created, which is divided in frames F1, F2, . . . of a predefined duration. By referring e.g. to the frame F1 shown in FIG. 6a, the serdes inserts in the frame F1 an alignment word AW′. Then, from time t10 to time t11, the serdes copies bits from the first parallel data flow PF1 into the frame F1, thus inserting into the frame F1 a copy S11 of a bit sequence S′11 of the first parallel data flow PF1. Then, from time t11 to time t12, the serdes copies bits from the second parallel data flow PF2 into the frame F1, thus inserting into the frame F1 a copy S12 of a bit sequence S′12 of the second parallel data flow PF2. Then, from time t12 to time t13, the serdes copies bits from the third parallel data flow PF3 into the frame F1, thus inserting into the frame F1 a copy S13 of a bit sequence S′13 of the third parallel data flow PF3. Then, from time t13 to time t14, the serdes copies bits from the fourth parallel data flow PF4 into the frame F1, thus inserting into the frame F1 a copy S14 of a bit sequence S′14 of the fourth parallel data flow PF4. The serdes then cyclically repeats the above procedure, thus forming the frame F2 of FIG. 6a and the successive frames, that for simplicity are not shown in FIG. 6a. 
The parallel data flows PF1, PF2, PF3, PF4 and the additional flow AF are then transmitted each on a respective physical connection of the parallel bus.
At the receiving side, the parallel data flows PF1, PF2, PF3, PF4 and the additional flow AF are in general non-aligned, due to skew. This situation is shown in FIG. 6b. The additional flow AF is therefore read, by considering each sequence S11, S12, S13, S14 and by searching the corresponding sequence S′11, S′12, S′13, S′14 in the parallel data flow PF1, PF2, PF3, PF4, respectively. When the corresponding sequences S′11, S′12, S′13, S′14 are found, the parallel data flows PF1, PF2, PF3, PF4 are time-shifted as indicated by the arrows in FIG. 6b, for aligning the corresponding sequences S′11, S′12, S′13, S′14 to the sequences S11, S12, S13, S14 of the additional flow AF, respectively. This procedure is cyclically repeated for each parallel data flow upon alignment is found, each time a frame of the additional flow AF is received. Alignment procedure is completed when all parallel data flows are individually aligned. After successful alignment, the alignment is continuously checked.